An 8T SRAM Array with Configurable Word Lines for In-Memory Computing Operation

Simulation of 8T SRAM Array for Low Power Sensor Application

The sensor network has become an important aspect in the day today life because of its wide range of application from medical field to the military application. The raw data from sensor node are of large quantity and hence it is necessary to store these data bits. In this paper, design of optimized SRAM array for low power applications is implemented. SRAM cell is designed using 8T. In this, tr...

Design of Low Power Sram Memory Using 8t Sram Cell

Low power design has become the major challenge of present chip designs as leakage power has been rising with scaling of technologies. As modern technology is spreading fast, it is very important to design low power, high performance, and fast responding SRAM (Static Random Access Memory) since they are critical component in high performance processors. The Conventional 6T SRAM cell is very muc...

VLSI Architecture for an Efficient Memory Built in Self Test for Configurable Embedded SRAM Memory

Memories are the most dominating blocks present on a chip. All types of chips contain embedded memories such as a Read Only Memory (ROM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and flash memory. Testing of these memories is a very tedious and challenging job as area over head, testing time and cost of the test play an important role. In this work an efficient V...

Design And Implementation of 8T SRAM cell for Analysis of DC Noise Margin during Write Operation

This paper focuses on the DC noise margin analysis and read/write failure analysis of the proposed 8T low power SRAM cell. In the proposed structure two voltage sources, one connected with the Bit line and the other connected with the Bit bar line for reducing the voltage swing during the switching activity. These two extra voltage sources will control the voltage swing on the output node and i...

Sram System Design for Memory Based Computing